`timescale 10us/100ns


module debouncer(
	slow_clk,
	btn_in,
	btn_out
);


input wire	slow_clk;
input wire	btn_in;
output wire	btn_out;

reg	DFF_instDFF1;
reg	SYNTHESIZED_WIRE_5;
wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_6;
wire	SYNTHESIZED_WIRE_7;

assign	SYNTHESIZED_WIRE_6 = 1;
assign	SYNTHESIZED_WIRE_7 = 1;



assign	SYNTHESIZED_WIRE_0 =  ~DFF_instDFF1;



assign	btn_out = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_0;


always@(posedge slow_clk or negedge SYNTHESIZED_WIRE_6 or negedge SYNTHESIZED_WIRE_7)
begin
if (!SYNTHESIZED_WIRE_6)
	begin
	SYNTHESIZED_WIRE_5 <= 0;
	end
else
if (!SYNTHESIZED_WIRE_7)
	begin
	SYNTHESIZED_WIRE_5 <= 1;
	end
else
	begin
	SYNTHESIZED_WIRE_5 <= btn_in;
	end
end


always@(posedge slow_clk or negedge SYNTHESIZED_WIRE_6 or negedge SYNTHESIZED_WIRE_7)
begin
if (!SYNTHESIZED_WIRE_6)
	begin
	DFF_instDFF1 <= 0;
	end
else
if (!SYNTHESIZED_WIRE_7)
	begin
	DFF_instDFF1 <= 1;
	end
else
	begin
	DFF_instDFF1 <= SYNTHESIZED_WIRE_5;
	end
end


endmodule
